1. Field of the Invention
This invention relates to a semiconductor device and manufacturing method therefor, and particularly to technology useful for effectively realizing higher integration and higher functionality in a semiconductor device wherein a plurality of semiconductor elements (chips) is mounted in a single package.
2. Description of the Related Art
In FIG. 1 are diagrammed examples of semiconductor devices of the type described above.
In the examples diagrammed, semiconductor devices are represented wherein a plurality of semiconductor chips is mounted on one substrate. In the example in FIG. 1A, semiconductor chips 2 are mounted on both surfaces of a substrate 1; in the example in FIG. 1B, semiconductor chips 2 and 2a are mounted in a stacked configuration on one surface of the substrate 1; in the example in FIG. 1C, a plurality of semiconductor chips 2 is mounted in a plane on the substrate 1; and in the example in FIG. 1D, one semiconductor chip 2 is mounted on one surface of the substrate 1, while a plurality of semiconductor chips 2 is mounted on the other surface thereof. These examples are respectively diagrammed schematically.
On the surface of the substrate 1, wiring patterns are formed as appropriate. To the wiring patterns, the electrode terminals (not shown) of the semiconductor chips 2 and 2a are electrically connected by wire bonding. The electrical connections between the semiconductor chips and the wiring patterns are not limited to wire bonding connection, and flip chip connections or TAB connections or the like can also be used.
In a conventional semiconductor device as described above, the semiconductor chips 2 and 2a are mounted in a mounting surface of the substrate 1, wherefore, due to the fact that the substrate 1 is made in regular sizes, the number of semiconductor chips that can be mounted is limited, which is a disadvantage.
When the semiconductor chips 2 and 2a are mounted in a stack, as diagrammed in FIG. 1B, the upper chip 2 must be made smaller than the lower chip 2a by an amount necessary for the area which is required to make the wire bonding connections. For that reason, the mounting area for the upper chip 2 becomes smaller, and there is inherently a limit to the number of chips that can be stacked.
In this case, when flip chip connections are used, there is no need to provide a region for bonding as described above, wherefore it is possible to increase the number of mounted chip as compared to the case of wire bonding connection. However, other difficulties arise instead.
With flip chip mounting, in general, solder bumps or other metal bumps (electrode terminals) are formed on the electrode pads of the semiconductor chips, and connections are effected by thermally pressing these bumps down on corresponding electrode pads on a mounting substrate such as a printed circuit board. When this method is applied to a stacked chip configuration as diagrammed in FIG. 1B, the upper chip 2 will be flip-chip connected to the lower chip 2a. In this case, it is necessary to form the electrode pads on the upper surface of the lower chip 2a so as to correspond with the positions of the bumps that are the electrode terminals of the upper chip 2. Also, when stacking the chips, alignment must be effected between the bumps on the upper chip and the electrode pads on the lower chip, making the overall process complex, which is a disadvantage.
When mounting a plurality of semiconductor chips in a single package in this manner, with a method as diagrammed in FIG. 1 in which the semiconductor chips 2 and 2a are simply mounted on the mounting surface or surfaces of the substrate 1, the number of semiconductor chips that are mounted is limited, and it is not always possible to realize adequately high integration and functionality.
That being so, in terms of a method for effecting higher integration and higher functionality, semiconductor device configurations have been devised in which the substrate is made in multiple layers, and semiconductor elements are provided inside the substrate. If use is made of a multi-layer substrate structure wherein a plurality of wiring layers is provided, for example, it is possible to electrically interconnect the semiconductor chips and deploy them three-dimensionally inside the substrate. It is not necessarily easy, however, to imbed the semiconductor chips inside the substrate and form the wiring layers in multiple layers. When the recent demands for making packages smaller and lighter in weight are taken into consideration, furthermore, there are problems which must be faced, such as the necessity of forming the semiconductor devices compactly with the overall thickness thereof made thinner.